Field of the Invention
The invention relates in general to the field of semiconductors, and specifically to a method for ensuring that the capacitance of a storage capacitor does not decrease when the integration level is increased, and even more specifically to a method for producing a memory cell with a storage capacitor having an electrode surface area that is greater than the surface area of the individual memory cell.
A memory cell having a storage capacitor with an electrode designed virtually as a planar plate and being configured parallel to a main surface area of the memory configuration is disclosed in Muller, "Bauelemente der Halbleiterelektronik", [Components of semiconductor electronics], Springer, 4th edition, 1991, 256 ff. The capacitance of a storage capacitor is a function of the capacitor area and would ordinarily become smaller with an increased integration level and the associated reduction in size of the memory configuration. To address this problem, the abovementioned document proposes the design of a storage capacitor as a trench capacitor that is configured like a pot in a main area of a memory configuration. The latter discussed design for realizing a storage capacitor has a considerably greater outlay than the former discussed design for a storage capacitor.
A further possibility for maintaining a specific capacitor area with an increased integration level is shown in U.S. Pat. No. 5,290,726. This document describes a design of the storage capacitor as a fin stacked capacitor which is configured over the selection transistor of the memory cell. In this design, a first electrode of the storage capacitor has a cross-section with a plurality of fingers lying next to one another and above one another, in order to increase the electrode surface area and hence the capacitor area in comparison with a plate-like design of the first electrode. This design of the storage capacitor requires a certain minimum area above the selection transistor within which the capacitor can be formed. As the integration level increases, it is difficult to provide this minimum area which is necessary for forming the capacitor. Furthermore, the capacitor structure described requires a very complicated production method.
European Patent Application EP 06 57 935 A2 discloses a semiconductor memory configuration and a method for the production of the semiconductor memory configuration. The memory configuration includes storage capacitors that have first electrodes designed as electrode plates that are configured at a distance one above the other as well as parallel to an upper main surface area of the semiconductor memory configuration. Each respective electrode plate is electrically connected to a respective selection transistor of a memory cell by a contact plug. In accordance with FIG. 3B of that document, the individual contact plugs are designed with different lengths corresponding to the distance to the respective electrode plate.
Japanese Patent Application JP 03-153074 A and Japanese Patent Application JP 62-179759 A describe semiconductor memory configurations having storage capacitors which have electrodes in plate form.